Types of ADCs: How They Work and What They’re Used For

Analog-to-digital converters (ADCs) are essential for bridging the analog and digital worlds and are used in a variety of applications. There are many types of ADCs, each with its own history, merits, and limitations. And each has favored applications based on its strengths and weaknesses. In this article, we’ll look at the most widely used ADC configurations: what they are, how they work, and what they’re used for.

In this article we’ll look at:

The most widely used types of ADCs

The table below summarizes the most widely used types of analog-to-digital converters (ADCs) and their strengths, weaknesses, and applications.

ADC TypeStrengthsWeaknessesApplications
Delta-sigmaHigh resolution and relatively inexpensiveRelatively slow and not suitable for high bandwidth applicationsPrecision DMMs, high-end data acquisition, pro-audio
FlashVery fastLarge, expensive, and power-hungryFast digital oscilloscopes, video digitization, RADAR, wideband radio
Successive approximation (SAR)Simple design, versatileNot very fast, limited resolution, susceptible to noiseIndustrial control and measurement, CMOS imaging
Voltage-to-frequency (integrating)Precise, inexpensive, high noise rejectionLow accuracyRemote sensing in noisy environments
Single-slope (integrating)Good resolutionLow accuracyDMMs and panel meters
Dual/multi-slope (integrating)Relatively slowGood accuracyPrecision DMMs
The most widely used types of ADCs: strengths, weaknesses, and applications

Let’s look at each of these in more detail.

Delta-sigma ADCs

We start by looking at delta-sigma ADCs (also referred to as ‘sigma-delta ADCs’)—a highly accurate and popular type of ADC, favored in many high-end applications including professional audio applications.

These ADCs are not very fast, but they are relatively inexpensive and support high resolutions—up to 32 bits—and make the most of both analog (fast) and digital (robust) circuitry. The delta-sigma approach is used successfully in both ADCs and DACs (digital-to-analog converters).

A key to delta-sigma’s success is that only the changes (delta) in values between consecutive samples are transmitted rather than the absolute values of the samples—this results in high transmission efficiency.

Applications include precision digital multimeters (DMMs), high-end data acquisition and communication systems, and (as mentioned) professional audio.

The concepts behind delta-sigma conversion

To understand how delta-sigma conversion works, you’ll need to be familiar with the concepts of quantization noise, oversampling, digital filtering, and noise shaping.

Quantization noise

Quantization noise results from the process of digitizing an analog signal. It’s caused by the loss of information (distortion) that occurs when converting a continuous signal to a discrete form.

The higher the bit-depth used for digitization, the lower the quantization noise due to the increased ‘granularity’ that a higher bit-depth allows.


Oversampling refers to using a higher sampling rate than necessary when digitizing a signal.

According to information theory, a sampling rate of at least twice the (highest) frequency of an analog input signal should be used to prevent aliasing (a type of distortion)—this is known as the Nyquist rate. So, oversampling refers to using a rate higher than the Nyquist rate.

Oversampling has the benefit of reducing the average quantization noise in the proximity (bandwidth) of a signal by spreading the noise energy over a wider frequency range than the Nyquist rate implies. This results in improving the relative energy between a digitized signal and its quantization noise, i.e., a higher signal-to-noise ratio or SNR.

Oversampling is usually done to a multiple of the Nyquist rate to maximize its benefits.

Digital filtering

Digital filtering refers to limiting the range of frequencies that pass through a system (i.e., filtering out unwanted frequencies) by using digital circuits.

When using oversampling, as mentioned, the average quantization noise is reduced by spreading it over a wider frequency range and improving the SNR. By applying a low-pass digital filter to an oversampled signal (i.e., allowing frequencies below a certain threshold to pass), only the frequency range that includes the main (digitized) signal is retained, with an improved SNR, and the unwanted frequency range (containing noise) is filtered out.

So, by applying digital filtering after oversampling, a digitized signal within the desired frequency range and with a sufficiently high SNR can be produced.

Noise shaping

Other than oversampling, we know that a higher bit-depth also reduces the quantization noise.

As it happens, there’s an approximate equivalence between oversampling by two times (2x) and a 0.5-bit increase in bit depth: both will improve the SNR by around 3 dB.

But this is before considering the impact of a technique known as noise shaping.

Noise shaping shifts most of the quantization noise to higher frequencies. So, after applying noise shaping, the amount of quantization noise in the vicinity of the main (digitized) signal’s frequency is reduced as most of the noise shifts to higher frequencies.

After applying both noise shaping and oversampling, therefore, the SNR improvement is much higher than 3 dB for a 2x increase in oversampling—it can be as high as 9 dB or 15 dB, for instance, depending on circuit design.

Bringing it all together—how delta-sigma conversion works

Delta-sigma conversion exploits all the techniques discussed above to produce excellent results.

And in practice, a bit-depth of only 1 is used in many delta-sigma ADCs.

Why only 1 bit?

Because it’s easy and inexpensive to build. It also keeps the circuit design simple. Adding just one more bit, for instance, introduces a range of design complexities.

And we know that even 1-bit is enough to produce a high SNR due to the combined effect of oversampling and noise shaping.

Bringing it all together, the basic operation of a delta-sigma ADC is summarized below.

Basic operation:

  • An input analog signal is converted to a bit-stream (typically 1-bit) by using an analog modulator
  • Oversampling, noise shaping, and low-pass digital filtering are done to reduce the average noise, push the noise out of the bit-stream’s signal bandwidth, and filter out the noise
  • Finally, decimation is applied (i.e., discarding samples beyond what’s required) to reduce the bit-stream’s high sample rate (due to oversampling) to a more usable data rate.


  • High accuracy and resolution
  • Well suited to hi-fidelity audio applications
  • Relatively inexpensive


  • Relatively slow
  • Generally not usable when more bandwidth is required (e.g., video applications)

Flash or ‘parallel’ ADCs

Flash ADCs are, perhaps, the simplest in concept of the ADCs and are very fast, but they tend to be large and expensive.

They derive their name from the parallel configuration of ‘comparator’ reference voltages used in the conversion process.

Typical applications include (fast) digital oscilloscopes, video digitization, (fast) optical storage, microwave measurements, fiber optics, RADAR detection, and wideband radio.

Basic operation:

  • The analog input voltage is compared with a set of (known) fixed reference voltages operating in parallel—the more reference voltages used, the better the resolution
  • To generate an n-bit result, 2n – 1 reference voltage comparators are required—e.g., 4-bit resolution requires 15 reference voltages, 8-bit resolution requires 255 reference voltages, and so on
  • One end of the comparator array is connected to the analog voltage, while the other end is connected to a series of resistors set up as voltage dividers


  • Fastest ADC method, capable of sampling rates in the gigahertz range


  • The higher the resolution, the larger the flash ADC needs to be, requiring more power and limiting the sample rate—an 8-bit resolution tends to achieve a sensible balance between power and precision and is a popular configuration
  • Larger and more expensive than other ADC configurations

Flash ADCs are often modified in practice, generally involving two or more stages of low-resolution, partial conversion to arrive at the required resolution (other than folding ADCs—see below)—this results in good performance with less power consumption than unmodified flash ADCs.

Common modifications:

  • Half-flash—a simple two-stage process involving, first, a flash conversion to half the required precision, which is converted back to analog (using an internal DAC), followed by a second flash conversion stage. These are low-cost converters that can operate with relatively low power.
  • Pipelined—a multistage process that extends the half-flash approach to ten or more successive conversions, resulting in higher resolutions than flash ADCs and using less power, but with slower speeds (although still very fast)
  • Folding—rather than a staged process, ‘folding circuits’ are used to reduce the number of comparators required (from 2n – 1 to 2n/m, where m is the number of folds) while achieving conversion in a single stage of repeating folds. These are less complex structures than flash or pipeline structures and, like half-flash, are lower in cost and power consumption.

Successive approximation (SAR) ADCs

As the name suggests, successive approximation ADCs work by running successive trials of internally generated voltages to compare with the analog input voltage. It requires n such trials to do an n-bit conversion. The acronym SAR refers to the successive approximation registers that help to generate the internal voltage trials.

SAR is a very popular ADC configuration since it offers a good balance between speed, resolution, and fidelity for a wide variety of signal types. They are slower than flash ADCs, however, since they must pause and reset after each trial.

Typical applications include data acquisition systems (DAQ), industrial control and measurement, and CMOS (digital camera and video) imaging.

Basic operation:

  • Successive trial codes are generated by internal logic circuitry and are converted to (analog) voltages by an internal DAC
  • The trial voltages are compared with the analog input voltage using a comparator
  • The trials get progressively closer to the level of the analog input voltage by testing whether they are above or below the midpoints of successively narrowing ranges


  • Relatively simple circuit design (only one comparator required)
  • Offers a good balance between speed and resolution
  • Versatile for different signal types (waveshapes)


  • Only intermediate speeds can be achieved (slower than flash but faster than delta-sigma ADCs)
  • Limited bit resolution—typically 8 to 18 bits—which is lower than delta-sigma ADCs
  • Not good at handling spikes in the analog input voltage
  • Requires separate (external) anti-aliasing filtering
  • Susceptible to high-frequency quantization noise

A common variation of SAR ADCs is tracking ADCs. These use an up-down counter to generate successive trial codes, producing faster results when the analog input voltage changes smoothly (but is slower when the analog input voltage experiences jumps).

Integrating ADCs

A family of converters known as integrating ADCs work by integrating (taking the average of) the analog input signal over a time period, i.e., either the time required to do a frequency count (voltage-to-frequency conversion) or to discharge a capacitor (single-slope, dual-slope, and multi-slope conversion).

Let’s take a closer look at these.

Voltage-to-frequency conversion

Voltage-to-frequency ADCs work by converting an analog input voltage to a pulse train whose frequency is proportional to the input voltage. These may be asynchronous, in which the pulses are generated internally and are unconstrained, or synchronous, requiring an external source of pulses.

These ADCs are precise, simple, and relatively inexpensive. But perhaps their key feature is their inherently high noise rejection characteristics. For this reason, they are widely used to convert slow and noisy signals. A common application is for remote sensing in noisy environments.

Single-slope integration

Single-slope ADCs exploit the proportionate relationship that exists between the time taken to charge a capacitor and its voltage level. If the voltage level is the analog input voltage, then the capacitor charge time (measured using an internal counter) is a digitization of the input voltage.

A comparator is used to identify when the capacitor’s voltage reaches the level of the analog input voltage, and when to stop the counter.

Although simple in concept, single-slope ADCs are not very accurate. This is because they rely heavily on the stability and accuracy of the capacitor and comparator used. These ADCs are, therefore, used in applications that don’t require a high degree of accuracy but need good resolution.

Dual-slope and multi-slope integration

The next two types of integrating ADCs— dual-slope and multi-slope—overcome the limitations of single-slope ADCs. They offer the following advantages:

  • Improved accuracy with less reliance on the stability of components used (capacitor and comparator)
  • Less sensitivity to interference from power sources (e.g., ‘hum’ from a 60 Hz power supply)

The improved accuracy of these ADCs results from using a ratio of values measured off the same capacitor, rather than an absolute value measured from a capacitor (as in single-slope ADCs).

The ratio is derived as follows: first, the ADC charges a capacitor with a current proportional to the level of the analog input voltage, then it measures the time required to discharge the same capacitor under a constant current—the ratio of the times for charge and discharge is what’s used to digitize the analog input voltage.

The reduced sensitivity to interference follows from the averaging approach (i.e., integration) used in these ADCs. By matching the integration time to a multiple of the power supply’s alternating current period, the ADC becomes insensitive to the effect of the power supply’s ‘hum’ and its harmonics.

While offering excellent precision, these ADCs are slower than successive approximation ADCs due to the time required for the integrating functions to occur.

Dual-slope ADCs

As noted above, dual-slope ADCs achieve very good accuracies without a heavy reliance on the stability of components used. But this comes at a cost: speed. Unlike successive approximation and delta-sigma ADCs (that can achieve both resolution and speed), there’s a trade-off between resolution and speed for dual-slope ADCs.

Nevertheless, the characteristics of dual-slope ADCs—accuracy, low interference sensitivity, and slow speed—make them an excellent choice for precision digital multimeters and panel meters, where accuracy rather than speed matters. Dual-slope ADCs can achieve a high degree of stability and accuracy in these applications (e.g., 20-bit) at a low cost, albeit slowly.

Multi-slope ADCs

In multi-slope ADCs, each conversion consists of several, fast dual-slope cycles. Corrections are made between successive cycles to further improve accuracy.

The multi-slope approach is even more tolerant of component imperfections than dual-slope and results in higher accuracy. Multi-slope ADCs are used in top-of-the-line digital multimeters (e.g., 8.5-digit multimeters) for this reason.


Analog-to-digital converters (ADCs) are essential for modern applications where analog and digital data come together. There are many types of ADCs, each suited for different applications based on their strengths and weaknesses.

In this article, we’ve looked at the most widely used types of ADCs, how they work, and where they are used.

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